The disclosure relates generally to improved routability of transistor placements, and more specifically, to field-effect transistor placement optimization for improved leaf cell routability.
In general, a topology of a chip includes a level hierarchy, usually nine to ten levels, which are built up from a first level (e.g., lowest negative metal-oxide-semiconductor (NMOS)/positive MOS (PMOS) level) by grouping cells of the previous level as the level hierarchy is ascended. Focusing on a second level of the level hierarchy, which can be referred to as a leaf cell level, NMOS/PMOS transistors of the first level are grouped within networks or nets. When planning a placement of the leaf cell level, competing placement requirements, such as area, interconnection length (which equates to timing), limited metal resources, electro-migration requirements, and external connection requirements, dictate the leaf cell level layout. Further, an area of the chip itself is a critical feature that relies on an efficient leaf cell layout and routability of this layout.
Presently, leaf cell level layout implementation is a bottleneck for bringing a chip to market. The bottleneck results partly from, when building a chip, some special circuits (e.g. dynamic logic in a static random access memory (SRAM) cannot be mapped to logic gates (e.g., NAND, NOR . . . ) from standard libraries. Conventional leaf layout generators automate the leaf cell level layout implementation to alleviate this bottleneck; however, conventional leaf layout generators fail to address issues, such as when the tightest placements are not routable and when advanced technology nodes pose more and more design constraints.